This invention relates to vertical field effect transistors.
Vertical junction field effect transistors are well known in the art. An example of such a transistor is discussed in U.S. Pat. No 4,476,622 issued to Cogan, and U.S. Pat. Nos. 4,543,706 and 4,566,172 issued to Bencuya, et al. In the processes discussed in these patents, an N- expitaxial layer is grown on an N+ substrate, and an N+ region is formed at the surface of the N- epitaxial layer. The N+ region serves as a transistor source and the N+ substrate serves as the drain. A plurality of grooves is then etched through the N+ layer and into a portion of the N- epitaxial layer. A P+ gate region is formed in the N- epitaxial layer at the bottom of the grooves. The size of the depletion region between the P+ gate region and the N- epitaxial layer is modulated by application of selected voltages to the P+ gate region. By modulating the size of this depletion region, the current between the N+ layer at the surface of the epitaxial layer and the N+ substrate can be controlled.